Hardware and Software: Verification and Testing Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007. Proceedings / [electronic resource] :
edited by Karen Yorav.
- Berlin, Heidelberg : Springer Berlin Heidelberg, 2008.
- XII, 267 p. online resource.
- Lecture Notes in Computer Science, 4899 0302-9743 ; .
- Lecture Notes in Computer Science, 4899 .
Invited Talks -- Simulation vs. Formal: Absorb What Is Useful; Reject What Is Useless -- Scaling Commercial Verification to Larger Systems -- From Hardware Verification to Software Verification: Re-use and Re-learn -- Where Do Bugs Come from? -- HVC Award -- Symbolic Execution and Model Checking for Testing -- Hardware Verification -- On the Characterization of Until as a Fixed Point Under Clocked Semantics -- Reactivity in SystemC Transaction-Level Models -- Model Checking -- Verifying Parametrised Hardware Designs Via Counter Automata -- How Fast and Fat Is Your Probabilistic Model Checker? An Experimental Performance Comparison -- Dynamic Hardware Verification -- Constraint Patterns and Search Procedures for CP-Based Random Test Generation -- Using Virtual Coverage to Hit Hard-To-Reach Events -- Merging Formal and Testing -- Test Case Generation for Ultimately Periodic Paths -- Dynamic Testing Via Automata Learning -- Formal Verification for Software -- On the Architecture of System Verification Environments -- Exploiting Shared Structure in Software Verification Conditions -- Delayed Nondeterminism in Model Checking Embedded Systems Assembly Code -- A Complete Bounded Model Checking Algorithm for Pushdown Systems -- Software Testing -- Locating Regression Bugs -- The Advantages of Post-Link Code Coverage -- GenUTest: A Unit Test and Mock Aspect Generation Tool.
9783540779667
10.1007/978-3-540-77966-7 doi
Computer science.
Software engineering.
Logic design.
Computer Science.
Software Engineering.
Logics and Meanings of Programs.
Programming Languages, Compilers, Interpreters.
QA76.758
005.1
Invited Talks -- Simulation vs. Formal: Absorb What Is Useful; Reject What Is Useless -- Scaling Commercial Verification to Larger Systems -- From Hardware Verification to Software Verification: Re-use and Re-learn -- Where Do Bugs Come from? -- HVC Award -- Symbolic Execution and Model Checking for Testing -- Hardware Verification -- On the Characterization of Until as a Fixed Point Under Clocked Semantics -- Reactivity in SystemC Transaction-Level Models -- Model Checking -- Verifying Parametrised Hardware Designs Via Counter Automata -- How Fast and Fat Is Your Probabilistic Model Checker? An Experimental Performance Comparison -- Dynamic Hardware Verification -- Constraint Patterns and Search Procedures for CP-Based Random Test Generation -- Using Virtual Coverage to Hit Hard-To-Reach Events -- Merging Formal and Testing -- Test Case Generation for Ultimately Periodic Paths -- Dynamic Testing Via Automata Learning -- Formal Verification for Software -- On the Architecture of System Verification Environments -- Exploiting Shared Structure in Software Verification Conditions -- Delayed Nondeterminism in Model Checking Embedded Systems Assembly Code -- A Complete Bounded Model Checking Algorithm for Pushdown Systems -- Software Testing -- Locating Regression Bugs -- The Advantages of Post-Link Code Coverage -- GenUTest: A Unit Test and Mock Aspect Generation Tool.
9783540779667
10.1007/978-3-540-77966-7 doi
Computer science.
Software engineering.
Logic design.
Computer Science.
Software Engineering.
Logics and Meanings of Programs.
Programming Languages, Compilers, Interpreters.
QA76.758
005.1