Parallel Computer Routing and Communication [electronic resource] : Second International Workshop, PCRCW’97 Atlanta, Georgia, USA, June 26–27, 1997 Proceedings / edited by Sudhakar Yalamanchili, José Duato.

Contributor(s): Yalamanchili, Sudhakar [editor.] | Duato, José [editor.] | SpringerLink (Online service)Material type: TextTextSeries: Lecture Notes in Computer Science ; 1417Publisher: Berlin, Heidelberg : Springer Berlin Heidelberg, 1998Description: XII, 309 pp. online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9783540693529Subject(s): Computer science | Memory management (Computer science) | Computer Communication Networks | Computer system performance | Computer software | Computer Science | Computer Communication Networks | Processor Architectures | Memory Structures | System Performance and Evaluation | Algorithm Analysis and Problem ComplexityAdditional physical formats: Printed edition:: No titleDDC classification: 004.6 LOC classification: TK5105.5-5105.9Online resources: Click here to access online
Contents:
Keynote Address -- Approaches to Quality of Service in High-Performance Networks -- Routing I -- Integrated Multi-class Routing -- Congestion Control in the Wormhole-Routed Torus With Clustering and Delayed Deflection -- Multicasting in Irregular Networks with Cut-Through Switches using Tree-Based Multidestination Worms* -- Poster Session -- CCSIMD: a Concurrent Communication and Computation Framework for SIMD Machines -- Arctic Switch Fabric -- Router and Network Architectures I -- STREAMER: Hardware Support for Smoothed Transmission of Stored Video over ATM -- Preliminary Evaluation of a Hybrid Deterministic/Adaptive Router -- HiPER-P: An Efficient, High-Performance Router for Multicomputer Interconnection Networks -- Router and Network Architectures II (Invited Presentations) -- ServerNet™ II -- Embedded Systems Standards -- Challenges in the Design of Contemporary Routers -- Panel Session -- Panel Session -- Messaging Layer Support -- Evaluation of Communication Mechanisms in Invalidate-based Shared Memory Multiprocessors -- How Can We Design Better Networks for DSM Systems? -- Integration of U-Net into Windows/NT -- Routing II -- Distance-Based Flow Control in Wormhole Networks -- On the Use of Virtual Channels in Networks of Workstations with Irregular Topology -- Multicasting on Switch-based Irregular Networks using Multi-drop Path-based Multidestination Worms -- Power/Performance Trade-offs for Direct Networks -- Router and Network Architectures III -- ChaosLAN: Design and Implementation of a Gigabit LAN Using Chaotic Routing -- Does Time-Division Multiplexing Close the Gap Between Memory and Optical Communication Speeds? -- Deadlock Issues -- Modeling Message Blocking and Deadlock in Interconnection Networks -- On the Reduction of Deadlock Frequency by Limiting Message Injection in Wormhole Networks.
In: Springer eBooksSummary: This workshop was a continuation of the PCRCW ’94 workshop that focused on issues in parallel communication and routing in support of parallel processing. The workshop series provides a forum for researchers and designers to exchange ideas with respect to challenges and issues in supporting communication for high-performance parallel computing. Within the last few years we have seen the scope of interconnection network technology expand beyond traditional multiprocessor systems to include high-availability clusters and the emerging class of system area networks. New application domains are creating new requirements for interconnection network services, e.g., real-time video, on-line data mining, etc. The emergence of quality-of-service guarantees within these domains challenges existing approaches to interconnection network design. In the recent past we have seen the emphasis on low-latency software layers, the application of multicomputer interconnection technology to distributed shared-memory multiprocessors and LAN interconnects, and the shift toward the use of commodity clusters and standard components. There is a continuing evolution toward powerful and inexpensive network interfaces, and low-cost, high-speed routers and switches from commercial vendors. The goal is to address the above issues in the context of networks of workstations, multicomputers, distributed shared-memory multiprocessors, and traditional tightly-coupled multiprocessor interconnects. The PCRCW ’97 workshop presented 20 regular papers and two short papers covering a range of topics dealing with modern interconnection networks. It was hosted by the Georgia Institute of Technology and sponsored by the Atlanta Chapter of the IEEE Computer Society.
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Keynote Address -- Approaches to Quality of Service in High-Performance Networks -- Routing I -- Integrated Multi-class Routing -- Congestion Control in the Wormhole-Routed Torus With Clustering and Delayed Deflection -- Multicasting in Irregular Networks with Cut-Through Switches using Tree-Based Multidestination Worms* -- Poster Session -- CCSIMD: a Concurrent Communication and Computation Framework for SIMD Machines -- Arctic Switch Fabric -- Router and Network Architectures I -- STREAMER: Hardware Support for Smoothed Transmission of Stored Video over ATM -- Preliminary Evaluation of a Hybrid Deterministic/Adaptive Router -- HiPER-P: An Efficient, High-Performance Router for Multicomputer Interconnection Networks -- Router and Network Architectures II (Invited Presentations) -- ServerNet™ II -- Embedded Systems Standards -- Challenges in the Design of Contemporary Routers -- Panel Session -- Panel Session -- Messaging Layer Support -- Evaluation of Communication Mechanisms in Invalidate-based Shared Memory Multiprocessors -- How Can We Design Better Networks for DSM Systems? -- Integration of U-Net into Windows/NT -- Routing II -- Distance-Based Flow Control in Wormhole Networks -- On the Use of Virtual Channels in Networks of Workstations with Irregular Topology -- Multicasting on Switch-based Irregular Networks using Multi-drop Path-based Multidestination Worms -- Power/Performance Trade-offs for Direct Networks -- Router and Network Architectures III -- ChaosLAN: Design and Implementation of a Gigabit LAN Using Chaotic Routing -- Does Time-Division Multiplexing Close the Gap Between Memory and Optical Communication Speeds? -- Deadlock Issues -- Modeling Message Blocking and Deadlock in Interconnection Networks -- On the Reduction of Deadlock Frequency by Limiting Message Injection in Wormhole Networks.

This workshop was a continuation of the PCRCW ’94 workshop that focused on issues in parallel communication and routing in support of parallel processing. The workshop series provides a forum for researchers and designers to exchange ideas with respect to challenges and issues in supporting communication for high-performance parallel computing. Within the last few years we have seen the scope of interconnection network technology expand beyond traditional multiprocessor systems to include high-availability clusters and the emerging class of system area networks. New application domains are creating new requirements for interconnection network services, e.g., real-time video, on-line data mining, etc. The emergence of quality-of-service guarantees within these domains challenges existing approaches to interconnection network design. In the recent past we have seen the emphasis on low-latency software layers, the application of multicomputer interconnection technology to distributed shared-memory multiprocessors and LAN interconnects, and the shift toward the use of commodity clusters and standard components. There is a continuing evolution toward powerful and inexpensive network interfaces, and low-cost, high-speed routers and switches from commercial vendors. The goal is to address the above issues in the context of networks of workstations, multicomputers, distributed shared-memory multiprocessors, and traditional tightly-coupled multiprocessor interconnects. The PCRCW ’97 workshop presented 20 regular papers and two short papers covering a range of topics dealing with modern interconnection networks. It was hosted by the Georgia Institute of Technology and sponsored by the Atlanta Chapter of the IEEE Computer Society.

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