| 000 -LEADER |
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| fixed length control field |
05201nam a22006015i 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| ISBN |
9783642115158 |
| -- |
978-3-642-11515-8 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
004 |
| 245 10 - TITLE STATEMENT |
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| Title |
High Performance Embedded Architectures and Compilers |
| Sub Title |
5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings / |
| Statement of responsibility, etc |
edited by Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell. |
| 260 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
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| Place of publication |
Berlin, Heidelberg : |
| Name of publisher |
Springer Berlin Heidelberg, |
| Year of publication |
2010. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Number of Pages |
XIII, 370 p. |
| Other physical details |
online resource. |
| 490 1# - SERIES STATEMENT |
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| Series statement |
Lecture Notes in Computer Science, |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Invited Program -- Embedded Systems as Datacenters -- Larrabee: A Many-Core Intel Architecture for Visual Computing -- Architectural Support for Concurrency -- Remote Store Programming -- Low-Overhead, High-Speed Multi-core Barrier Synchronization -- Improving Performance by Reducing Aborts in Hardware Transactional Memory -- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems -- Compilation and Runtime Systems -- Split Register Allocation: Linear Complexity Without the Performance Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors -- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures -- Reconfigurable and Customized Architectures -- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions -- Accelerating XML Query Matching through Custom Stack Generation on FPGAs -- An Application-Aware Load Balancing Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays -- Multicore Efficiency, Reliability, and Power -- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors -- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors -- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor -- Performance and Power Aware CMP Thread Allocation Modeling -- Memory Organization and Optimization -- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching -- Scalable Shared-Cache Management by Containing Thrashing Workloads -- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs -- DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems -- Programming and Analysis of Accelerators -- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor -- Analysis of Task Offloading for Accelerators -- Offload – Automating Code Migration to Heterogeneous Multicore Systems -- Computer Generation of Efficient Software Viterbi Decoders. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc |
This book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010. The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were carefully reviewed and selected from 94 submissions. The papers are organized in topical sections on architectural support for concurrency; compilation and runtime systems; reconfigurable and customized architectures; multicore efficiency, reliability, and power; memory organization and optimization; and programming and analysis of accelerators. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer science. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Data transmission systems. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Logic design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer Communication Networks. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer Science. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Arithmetic and Logic Structures. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Input/Output and Data Communications. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Logic Design. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer Communication Networks. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Programming Languages, Compilers, Interpreters. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Patt, Yale N. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Foglia, Pierfrancesco. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Duesterwald, Evelyn. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Faraboschi, Paolo. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Martorell, Xavier. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
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| Uniform Resource Identifier |
http://dx.doi.org/10.1007/978-3-642-11515-8 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Koha item type |
E-BOOKS |
| 264 #1 - |
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Berlin, Heidelberg : |
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Springer Berlin Heidelberg, |
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2010. |
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text |
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txt |
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rdacontent |
| 337 ## - |
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computer |
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c |
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rdamedia |
| 338 ## - |
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online resource |
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cr |
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rdacarrier |
| 347 ## - |
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text file |
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PDF |
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rda |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
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0302-9743 ; |
