High Performance Embedded Architectures and Compilers (Record no. 37292)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04600nam a22005895i 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783540775607 |
| -- | 978-3-540-77560-7 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 004 |
| 245 10 - TITLE STATEMENT | |
| Title | High Performance Embedded Architectures and Compilers |
| Sub Title | Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008. Proceedings / |
| Statement of responsibility, etc | edited by Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer. |
| 260 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | Berlin, Heidelberg : |
| Name of publisher | Springer Berlin Heidelberg, |
| Year of publication | 2008. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XIII, 400 p. |
| Other physical details | online resource. |
| 490 1# - SERIES STATEMENT | |
| Series statement | Lecture Notes in Computer Science, |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Invited Program -- Supercomputing for the Future, Supercomputing from the Past (Keynote) -- I Multithreaded and Multicore Processors -- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable - ASIP -- BRAM-LUT Tradeoff on a Polymorphic DES Design -- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array -- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP -- IIb Compiler Optimizations -- Fast Bounds Checking Using Debug Register -- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis -- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems -- III Industrial Processors and Application Parallelization -- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program on the Cell BE -- Drug Design Issues on the Cell BE -- IV Power-Aware Techniques -- Coffee: COmpiler Framework for Energy-Aware Exploration -- Integrated CPU Cache Power Management in Multiple Clock Domain Processors -- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation -- V High-Performance Processors -- The Significance of Affectors and Affectees Correlations for Branch Prediction -- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator -- LPA: A First Approach to the Loop Processor Architecture -- VI Profiles: Collection and Analysis -- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm -- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy -- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior -- VII Optimizing Memory Performance -- MLP-Aware Dynamic Cache Partitioning -- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture -- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory -- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Computer science. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Data transmission systems. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Logic design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Computer Communication Networks. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Computer Science. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Arithmetic and Logic Structures. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Input/Output and Data Communications. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Logic Design. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Computer Communication Networks. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Programming Languages, Compilers, Interpreters. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Stenström, Per. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Dubois, Michel. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Katevenis, Manolis. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Gupta, Rajiv. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Ungerer, Theo. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-3-540-77560-7 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | E-BOOKS |
| 264 #1 - | |
| -- | Berlin, Heidelberg : |
| -- | Springer Berlin Heidelberg, |
| -- | 2008. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| -- | 0302-9743 ; |
| Withdrawn status | Lost status | Damaged status | Not for loan | Current library | Accession Number | Uniform Resource Identifier | Koha item type |
|---|---|---|---|---|---|---|---|
| IMSc Library | EBK7998 | http://dx.doi.org/10.1007/978-3-540-77560-7 | E-BOOKS |