Transactions on High-Performance Embedded Architectures and Compilers I (Record no. 36824)

000 -LEADER
fixed length control field 03562nam a22005415i 4500
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783540715283
-- 978-3-540-71528-3
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 004
245 10 - TITLE STATEMENT
Title Transactions on High-Performance Embedded Architectures and Compilers I
Statement of responsibility, etc edited by Per Stenström.
260 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication Berlin, Heidelberg :
Name of publisher Springer Berlin Heidelberg,
Year of publication 2007.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XVI, 368 p.
Other physical details online resource.
490 1# - SERIES STATEMENT
Series statement Lecture Notes in Computer Science,
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note High Performance Processor Chips -- High Performance Processor Chips -- High-Performance Embedded Architecture and Compilation Roadmap -- 1: First International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2005. Best Papers -- to Part 1 -- Quick and Practical Run-Time Evaluation of Multiple Program Optimizations -- Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems -- GCH: Hints for Triggering Garbage Collections -- Memory-Centric Security Architecture -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- 2: Optimizing Compilers -- to Part 2 -- Convergent Compilation Applied to Loop Unrolling -- Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations -- Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures -- Automatic Discovery of Coarse-Grained Parallelism in Media Applications -- An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors -- 3: ACM International Conference on Computing Frontiers 2006. Best Papers -- to Part 3 -- Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology -- Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture -- Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors -- Selective Code Compression Scheme for Embedded Systems -- A Prefetching Algorithm for Multi-speed Disks -- Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Computer science.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Data transmission systems.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Logic design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Computer Communication Networks.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Computer Science.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Arithmetic and Logic Structures.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Processor Architectures.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Input/Output and Data Communications.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Logic Design.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Computer Communication Networks.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Programming Languages, Compilers, Interpreters.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Stenström, Per.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/978-3-540-71528-3
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type E-BOOKS
264 #1 -
-- Berlin, Heidelberg :
-- Springer Berlin Heidelberg,
-- 2007.
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-- computer
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-- rdamedia
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-- online resource
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-- text file
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830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
-- 0302-9743 ;
Holdings
Withdrawn status Lost status Damaged status Not for loan Current library Accession Number Uniform Resource Identifier Koha item type
        IMSc Library EBK7530 http://dx.doi.org/10.1007/978-3-540-71528-3 E-BOOKS
The Institute of Mathematical Sciences, Chennai, India

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