| 000 -LEADER |
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| fixed length control field |
07154nam a22005175i 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| ISBN |
9783540487838 |
| -- |
978-3-540-48783-8 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.395 |
| 245 10 - TITLE STATEMENT |
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| Title |
Field-Programmable Logic Architectures, Synthesis and Applications |
| Sub Title |
4th International Workshop on Field-Programmable Logic and Applications, FPL'94 Prague, Czech Republic, September 7–9, 1994 Proceedings / |
| Statement of responsibility, etc |
edited by Reiner W. Hartenstein, Michal Z. Servít. |
| 260 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication |
Berlin, Heidelberg : |
| Name of publisher |
Springer Berlin Heidelberg, |
| Year of publication |
1994. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Number of Pages |
XIII, 439 p. |
| Other physical details |
online resource. |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Lecture Notes in Computer Science, |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Fault modeling and test generation for FPGAs -- A test methodology applied to Cellular logic Programmable Gate Arrays -- Integrated layout synthesis for FPGA's -- Influence of logic block layout architecture on FPGA performance -- A global routing heuristic for FPGAs based on mean field annealing -- Power dissipation driven FPGA place and route under delay constraints -- FPGA technology mapping for power minimization -- Specification and synthesis of complex arithmetic operators for FPGAs -- A speed-up technique for synchronous circuits realized as LUT-based FPGAs -- An efficient technique for mapping RTL structures onto FPGAs -- A testbench design method suitable for FPGA-based prototyping of reactive systems -- Using consensusless covers for fast operating on Boolean functions -- Formal verification of timing rules in design specifications -- Optimized synthesis of self-testable finite state machines (FSM) using BIST-PST structures in Altera structures -- A high-speed rotation processor -- The MD5 message-digest algorithm in the XILINX FPGA -- A reprogrammable processor for fractal image compression -- Implementing GCD systolic Arrays on FPGA -- Formal CAD techniques for safety-critical FPGA design and deployment in embedded subsystems -- Direct sequence spread spectrum digital Radio DSP prototyping using xilinx FPGAs -- FPGA based reconfigurable architecture for a compact vision system -- A new FPGA architecture for word-oriented datapaths -- Image processing on a custom computing platform -- A superscalar and reconfigurable processor -- A fast FPGA implementation of a general purpose neuron -- Data-procedural languages for FPL-based machines -- Implementing on line arithmetic on PAM -- Software environment for WASMII: A data driven machine with a virtual hardware -- Constraint-based hierarchical placement of parallel programs -- ZAREPTA: A zero lead-time, all reconfigurable system for emulation, prototyping and testing of ASICs -- Simulating static and dynamic faults in BIST structures with a FPGA based emulator -- FPGA based prototyping for verification and evaluation in hardware-software cosynthesis -- FPGA based low cost Generic Reusable Module for the rapid prototyping of subsystems -- FPGA development tools: Keeping pace with design complexity -- Meaningful benchmarks for logic optimization of table-lookup FPGAs -- Educational use of Field Programmable Gate Arrays -- Hardwire: A risk-free FPGA-to-ASIC migration path -- Reconfigurable hardware from programmable logic devices -- On some limits of XILINX based control logic implementations -- Experiences of using XBLOX for implementing a digital filter algorithm -- Continuous interconnect provides solution to density/performance trade-off in programmable logic -- A high density complex PLD family optimized for flexibility, predictability and 100% routability -- Design experience with fine-grained FPGAs -- FPGA routing structures from real circuits -- A tool-set for simulating altera-PLDs using VHDL -- A CAD tool for the development of an Extra-Fast Fuzzy Logic Controller based on FPGAs and memory modules -- Performance characteristics of the Monte-Carlo clustering processor (MCCP) - a field programmable logic based custom computing machine -- A Design Environment with Emulation of Prototypes for hardware/software systems using XILINX FPGA -- DSP development with full-speed prototyping based on HW/SW codesign techniques -- The architecture of a general-purpose processor cell -- The design of a stack-based microprocessor -- Implementation and performance evaluation of an image pre-processing chain on FPGA -- Signature testability of PLA -- A FPL prototyping package with a C++ interface for the PC bus -- Design of safety systems using Field Programmable Gate Arrays -- A job dispatcher-collector made of FPGA's for a centralized Voice Server -- An optoelectronic 3-D Field Programmable Gate Array -- On channel architecture and routability for FPGA's under faulty conditions -- High-performance datapath implementation on Field-Programmable Multi-Chip Module (FPMCM) -- A laboratory for a digital design course using FPGAs -- Coordinate Rotation DIgital Computer (CORDIC) synthesis for FPGA -- MARC: A Macintosh NUBUS-expansion board based reconfigurable test system for validating communication systems -- Artificial neural network implementation on a fine-grained FPGA. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
This volume contains the proceedings of the 4th International Workshop on Field-Programmable Logic and Applications (FPL '94), held in Prague, Czech Republic in September 1994. The growing importance of field-programmable devices is substantiated by the remarkably high number of 116 submissions for FPL '94; from them, the revised versions of 40 full papers and 24 high-quality poster presentations were accepted for inclusion in this volume. Among the topics treated are: testing, layout, synthesis tools, compilation research and CAD, trade-offs and experience, innovations and smart applications, FPGA-based computer architectures, high-level design, prototyping and ASIC emulators, commercial devices, new tools, CCMs and HW/SW co-design, modelers, educational experience, and novel architectures. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer science. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical Term |
Logic design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer aided design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Electronics. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical Term |
Computer Science. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Logic Design. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Electronics and Microelectronics, Instrumentation. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer-Aided Engineering (CAD, CAE) and Design. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Hartenstein, Reiner W. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Servít, Michal Z. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
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| Uniform Resource Identifier |
http://dx.doi.org/10.1007/3-540-58419-6 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Koha item type |
E-BOOKS |
| 264 #1 - |
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Berlin, Heidelberg : |
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Springer Berlin Heidelberg, |
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1994. |
| 336 ## - |
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text |
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rdacontent |
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computer |
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c |
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rdamedia |
| 338 ## - |
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online resource |
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cr |
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rdacarrier |
| 347 ## - |
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text file |
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PDF |
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rda |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
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0302-9743 ; |
