| 000 -LEADER |
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| fixed length control field |
05430nam a22005535i 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| ISBN |
9783540409229 |
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978-3-540-40922-9 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
004 |
| 245 10 - TITLE STATEMENT |
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| Title |
Formal Methods in Computer-Aided Design |
| Sub Title |
Third International Conference, FMCAD 2000 Austin, TX, USA, November 1–3, 2000 Proceedings / |
| Statement of responsibility, etc |
edited by Warren A. Hunt, Steven D. Johnson. |
| 260 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
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| Place of publication |
Berlin, Heidelberg : |
| Name of publisher |
Springer Berlin Heidelberg, |
| Year of publication |
2000. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Number of Pages |
XII, 552 p. |
| Other physical details |
online resource. |
| 490 1# - SERIES STATEMENT |
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| Series statement |
Lecture Notes in Computer Science, |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Applications of Hierarchical Verification in Model Checking -- Applications of Hierarchical Verification in Model Checking -- Invited Talk -- Trends in Computing -- Invited Paper -- A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon TM Processor -- Contributed Papers -- An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps -- Automated Refinement Checking for Asynchronous Processes -- Border-Block Triangular Form and Conjunction Schedule in Image Computation -- B2M: A Semantic Based Tool for BLIF Hardware Descriptions -- Checking Safety Properties Using Induction and a SAT-Solver -- Combining Stream-Based and State-Based Verification Techniques -- A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles -- Correctness of Pipelined Machines -- Do You Trust Your Model Checker? -- Executable Protocol Specification in ESL -- Formal Verification of Floating Point Trigonometric Functions -- Hardware Modeling Using Function Encapsulation -- A Methodology for the Formal Analysis of Asynchronous Micropipelines -- A Methodology for Large-Scale Hardware Verification -- Model Checking Synchronous Timing Diagrams -- Model Reductions and a Case Study -- Modeling and Parameters Synthesis for an Air TrafficManagement System -- Monitor-Based Formal Specification of PCI -- SAT-Based Image Computation with Application in Reachability Analysis -- SAT-Based Verification without State Space Traversal -- Scalable Distributed On-the-Fly Symbolic Model Checking -- The Semantics of Verilog Using Transition System Combinators -- Sequential Equivalence Checking by Symbolic Simulation -- Speeding Up Image Computation by Using RTL Information -- Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs -- Symbolic Simulation with Approximate Values -- A Theory of Consistency for Modular Synchronous Systems -- Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods -- Visualizing System Factorizations with Behavior Tables. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc |
The biannual Formal Methods in Computer Aided Design conference (FMCAD 2000)is the third in a series of conferences under that title devoted to the use of discrete mathematical methods for the analysis of computer hardware and so- ware. The work reported in this book describes the use of modeling languages and their associated automated analysis tools to specify and verify computing systems. Functional veric ation has become one of the principal costs in a modern computer design e ort. In addition,verica tion of circuit models, timing,power, etc., requires even more eo rt. FMCAD provides a venue for academic and - dustrial researchers and practitioners to share their ideas and experiences of using discrete mathematical modeling and veric ation. It is noted with interest by the conference chairmen how this area has grown from just a few people 15 years ago to a vibrant area of research, development, and deployment. It is clear that these methods are helping reduce the cost of designing computing systems. As an example of this potential cost reduction, we have invited David Russino of Advanced Micro Devices, Inc. to describe his veric ation of ?oating-point - gorithms being used in AMD microprocessors. The program includes 30 regular presentations selected from 63 submitted papers. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer science. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer hardware. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Logic design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Artificial intelligence. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer Science. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer Hardware. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Logics and Meanings of Programs. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Mathematical Logic and Formal Languages. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Artificial Intelligence (incl. Robotics). |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Systems and Information Theory in Engineering. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Hunt, Warren A. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Johnson, Steven D. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
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| Uniform Resource Identifier |
http://dx.doi.org/10.1007/3-540-40922-X |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Koha item type |
E-BOOKS |
| 264 #1 - |
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Berlin, Heidelberg : |
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Springer Berlin Heidelberg, |
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2000. |
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online resource |
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text file |
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PDF |
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rda |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
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0302-9743 ; |
