High Performance Embedded Architectures and Compilers (Record no. 33232)

000 -LEADER
fixed length control field 05507nam a22006015i 4500
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783540322726
-- 978-3-540-32272-6
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 004
245 10 - TITLE STATEMENT
Title High Performance Embedded Architectures and Compilers
Sub Title First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005. Proceedings /
Statement of responsibility, etc edited by Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer.
260 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication Berlin, Heidelberg :
Name of publisher Springer Berlin Heidelberg,
Year of publication 2005.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XIV, 318 p.
Other physical details online resource.
490 1# - SERIES STATEMENT
Series statement Lecture Notes in Computer Science,
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Invited Program -- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications -- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges -- Software Defined Radio – A High Performance Embedded Challenge -- I Analysis and Evaluation Techniques -- A Practical Method for Quickly Evaluating Program Optimizations -- Efficient Sampling Startup for Sampled Processor Simulation -- Enhancing Network Processor Simulation Speed with Statistical Input Sampling -- II Novel Memory and Interconnect Architectures -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation -- Streaming Sparse Matrix Compression/Decompression -- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs -- III Security Architecture -- Memory-Centric Security Architecture -- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management -- Arc3D: A 3D Obfuscation Architecture -- IV Novel Compiler and Runtime Techniques -- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations -- Induction Variable Analysis with Delayed Abstractions -- Garbage Collection Hints -- V DomainSpecificArchitectures -- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors -- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture -- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems -- A Low-Power DSP-Enhanced 32-Bit EISC Processor.
520 ## - SUMMARY, ETC.
Summary, etc As Chairmen of HiPEAC 2005, we have the pleasure of welcoming you to the proceedings of the ?rst international conference promoted by the HiPEAC N- work of Excellence. During the last year, HiPEAC has been building its clusters of researchers in computer architecture and advanced compiler techniques for embedded and high-performance computers. Recently, the Summer School has been the seed for a fruitful collaboration of renowned international faculty and young researchers from 23 countries with fresh new ideas. Now, the conference promises to be among the premier forums for discussion and debate on these research topics. Theprestigeofasymposiumismainlydeterminedbythequalityofitstech- cal program. This ?rst programlived up to our high expectations, thanks to the largenumber of strong submissions. The ProgramCommittee received a total of 84 submissions; only 17 were selected for presentation as full-length papers and another one as an invited paper. Each paper was rigorously reviewed by three ProgramCommittee members and at least one external referee. Many reviewers spent a great amount of e?ort to provide detailed feedback. In many cases, such feedback along with constructive shepherding resulted in dramatic improvement in the quality of accepted papers. The names of the Program Committee m- bers and the referees are listed in the proceedings. The net result of this team e?ort is that the symposium proceedings include outstanding contributions by authors from nine countries in three continents. In addition to paper presentations, this ?rst HiPEAC conference featured two keynotes delivered by prominent researchers from industry and academia.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Computer science.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Data transmission systems.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Logic design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Computer Communication Networks.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Computer Science.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Arithmetic and Logic Structures.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Input/Output and Data Communications.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Logic Design.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Processor Architectures.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Computer Communication Networks.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Programming Languages, Compilers, Interpreters.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Conte, Tom.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Navarro, Nacho.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Hwu, Wen-mei W.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Valero, Mateo.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Ungerer, Theo.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/11587514
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type E-BOOKS
264 #1 -
-- Berlin, Heidelberg :
-- Springer Berlin Heidelberg,
-- 2005.
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-- computer
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-- rdamedia
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-- online resource
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-- text file
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830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
-- 0302-9743 ;
Holdings
Withdrawn status Lost status Damaged status Not for loan Current library Accession Number Uniform Resource Identifier Koha item type
        IMSc Library EBK3938 http://dx.doi.org/10.1007/11587514 E-BOOKS
The Institute of Mathematical Sciences, Chennai, India

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