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04476nam a22005775i 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| ISBN |
9783540320807 |
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978-3-540-32080-7 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.395 |
| 245 10 - TITLE STATEMENT |
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| Title |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation |
| Sub Title |
15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings / |
| Statement of responsibility, etc |
edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest. |
| 260 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
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| Place of publication |
Berlin, Heidelberg : |
| Name of publisher |
Springer Berlin Heidelberg, |
| Year of publication |
2005. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Number of Pages |
XVI, 756 p. |
| Other physical details |
online resource. |
| 490 1# - SERIES STATEMENT |
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| Series statement |
Lecture Notes in Computer Science, |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Session 1: Low-Power Processors -- Session 2: Code Optimization for Low-Power -- Session 3: High-Level Design -- Session 4: Telecommunications and Signal Processing -- Session 5: Low-Power Circuits -- Session 6: System-on-Chip Design -- Session 7: Busses and Interconnections -- Session 8: Modeling -- Session 9: Design Automation -- Session 10: Low-Power Techniques -- Session 11: Memory and Register Files -- Poster Session 1: Applications -- Poster Session 2: Digital Circuits -- Poster Session 3: Analog and Physical Design -- Special Session: Digital Hearing Aids: Challenges and Solutions for Ultra Low Power -- Invited Talks. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc |
Welcome to the proceedings of PATMOS 2005, the 15th in a series of international workshops.PATMOS2005wasorganizedbyIMECwithtechnicalco-sponsorshipfrom the IEEE Circuits and Systems Society. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the developmentof upcominggenerationsof integrated circuits and systems. The technical program of PATMOS 2005 contained state-of-the-art technical contri- tions, three invited talks, a special session on hearing-aid design, and an embedded - torial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, char- terization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert revi- ers, selected the 74 papers to be presented at PATMOS. The papers were divided into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were carried out per paper. Beyond the presentations of the papers, the PATMOS technical program was - riched by a series of speeches offered by world class experts, on important emerging research issues of industrial relevance. Prof. Jan Rabaey, Berkeley, USA, gave a talk on “Traveling the Wild Frontier of Ulta Low-Power Design”, Dr. Sung Bae Park, S- sung, gave a presentation on “DVL (Deep Low Voltage): Circuits and Devices”, Prof. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer science. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Logic design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Operating systems (Computers). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer aided design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer engineering. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer Science. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Logic Design. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Performance and Reliability. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Arithmetic and Logic Structures. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Computer-Aided Engineering (CAD, CAE) and Design. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
Electrical Engineering. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Paliouras, Vassilis. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Vounckx, Johan. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Verkest, Diederik. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
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| Uniform Resource Identifier |
http://dx.doi.org/10.1007/11556930 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Koha item type |
E-BOOKS |
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Berlin, Heidelberg : |
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Springer Berlin Heidelberg, |
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2005. |
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online resource |
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text file |
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PDF |
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| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
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0302-9743 ; |
