000 06893nam a22006855i 4500
001 978-3-319-30695-7
003 DE-He213
005 20210120143304.0
007 cr nn 008mamaa
008 160330s2016 gw | s |||| 0|eng d
020 _a9783319306957
_9978-3-319-30695-7
024 7 _a10.1007/978-3-319-30695-7
_2doi
050 4 _aTK5105.5-5105.9
072 7 _aUKN
_2bicssc
072 7 _aCOM075000
_2bisacsh
072 7 _aUKN
_2thema
082 0 4 _a004.6
_223
245 1 0 _aArchitecture of Computing Systems -- ARCS 2016
_h[electronic resource] :
_b29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings /
_cedited by Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich.
250 _a1st ed. 2016.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2016.
300 _aXX, 402 p. 164 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aTheoretical Computer Science and General Issues ;
_v9637
_aLecture Notes in Computer Science
_v9637
505 0 _aConfigurable and In-Memory Accelerators -- Towards Multicore Performance with Configurable Computing Units -- Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube -- Network-on-Chip and Secure Computing Architectures -- CASCADE: Congestion Aware Switchable Cycle Adaptive Detection Router -- An Alternating Transmission Scheme for Detection Routing based Network-on-Chips -- Exzess: Hardware-based RAM Encryption against Physical Memory Disclosure -- Hardware-Assisted Context Management for Accelerator Virtualization: A Case Study with RSA -- Cache Architectures and Protocols Adaptive Cache Structures -- Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence -- Mapping of Applications on Heterogeneous -- Architectures and Real-Time Tasks on Multiprocessors Generic algorithmic scheme for 2D stencil applications on heterogeneous hybrid machines -- GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing -- Task Variants with Different Scratchpad Memory Consumption in Multi-Task Environments -- Feedback-Based Admission Control for Hard Real-Time Task Allocation under Dynamic Workload on Many-core Systems -- All About Time: Timing, Tracing, and Performance Modeling Data Age Diminution in the Logical Execution Time Model -- Accurate Sample Time Reconstruction for Sensor Data Synchronization -- DiaSys: On-Chip Trace Analysis for Multi-Processor System-on-Chip -- Analysis of Intel's Haswell Microarchitecture Using The ECM Model and Microbenchmarks -- Measurement-Based Probabilistic Timing Analysis for Graphics Processor Units -- Approximate and Energy-Efficient Computing -- Reducing Energy Consumption of Data Transfers using Runtime Data Type Conversion -- Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector -- Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-based Modeling -- Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting -- Allocation: From Memories to FPGA Hardware Modules Reducing NoC and Memory Contention for Manycores -- An Efficient Data Structure for Dynamic Two-Dimensional Reconfiguration -- Organic Computing Systems Runtime Clustering of Similarly Behaving Agents in Open Organic Computing Systems -- Comparison of Dependency Measures for the Detection of Mutual Influences in Organic Computing Systems -- Augmenting the Algorithmic Structure of XCS by Means of Interpolation -- Reliability Aspects in NoCs, Caches, and GPUs Estimation of End-to-end Packet Error Rates for NoC Multicasts -- Protecting Code Regions on Asymmetrically Reliable Caches -- A New Simulation-based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs.
520 _aThis book constitutes the proceedings of the 29th International Conference on Architecture of Computing Systems, ARCS 2016, held in Nuremberg, Germany, in April 2016. The 29 full papers presented in this volume were carefully reviewed and selected from 87 submissions. They were organized in topical sections named: configurable and in-memory accelerators; network-on-chip and secure computing architectures; cache architectures and protocols; mapping of applications on heterogeneous architectures and real-time tasks on multiprocessors; all about time: timing, tracing, and performance modeling; approximate and energy-efficient computing; allocation: from memories to FPGA hardware modules; organic computing systems; and reliability aspects in NoCs, caches, and GPUs.
650 0 _aComputer communication systems.
650 0 _aArchitecture, Computer.
650 0 _aAlgorithms.
650 0 _aSoftware engineering.
650 0 _aApplication software.
650 0 _aComputers.
650 1 4 _aComputer Communication Networks.
_0https://scigraph.springernature.com/ontologies/product-market-codes/I13022
650 2 4 _aComputer System Implementation.
_0https://scigraph.springernature.com/ontologies/product-market-codes/I13057
650 2 4 _aAlgorithm Analysis and Problem Complexity.
_0https://scigraph.springernature.com/ontologies/product-market-codes/I16021
650 2 4 _aSoftware Engineering.
_0https://scigraph.springernature.com/ontologies/product-market-codes/I14029
650 2 4 _aInformation Systems Applications (incl. Internet).
_0https://scigraph.springernature.com/ontologies/product-market-codes/I18040
650 2 4 _aComputation by Abstract Devices.
_0https://scigraph.springernature.com/ontologies/product-market-codes/I16013
700 1 _aHannig, Frank.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aCardoso, João M.P.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aPionteck, Thilo.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aFey, Dietmar.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aSchröder-Preikschat, Wolfgang.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aTeich, Jürgen.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
710 2 _aSpringerLink (Online service)
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783319306940
776 0 8 _iPrinted edition:
_z9783319306964
830 0 _aTheoretical Computer Science and General Issues ;
_v9637
830 0 _aLecture Notes in Computer Science ;
_v9637
856 4 0 _uhttps://doi.org/10.1007/978-3-319-30695-7
912 _aZDB-2-SCS
912 _aZDB-2-SXCS
912 _aZDB-2-LNC
942 _cEBK
999 _c57095
_d57095