000 04425nam a22005895i 4500
001 978-3-540-70655-7
003 DE-He213
005 20160624102102.0
007 cr nn 008mamaa
008 121227s1993 gw | s |||| 0|eng d
020 _a9783540706557
_9978-3-540-70655-7
024 7 _a10.1007/BFb0021709
_2doi
050 4 _aQA76.635
072 7 _aUMB
_2bicssc
072 7 _aCOM067000
_2bisacsh
072 7 _aCOM041000
_2bisacsh
082 0 4 _a005.18
_223
245 1 0 _aCorrect Hardware Design and Verification Methods
_h[electronic resource] :
_bIFIPWG10.2 Advanced Research Working Conference, CHARME'93 Arles France May 24–26, 1993 Proceedings /
_cedited by George J. Milne, Laurence Pierre.
260 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1993.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1993.
300 _aIX, 275 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v683
505 0 _aA graph-based method for timing diagrams representation and verification -- A Petri Net approach for the analysis of VHDL descriptions -- Temporal analysis of time bounded digital systems -- Strongly-typed theory of structures and behaviours -- Verification and diagnosis of digital systems by ternary reasoning -- Logic verification of incomplete functions and design error location -- A methodology for system-level design for verifiability -- Algebraic models and the correctness of microprocessors -- Combining symbolic evaluation and object oriented approach for verifying processor-like architectures at the RT-level -- A theory of generic interpreters -- Towards verifying large(r) systems: A strategy and an experiment -- Advancements in symbolic traversal techniques -- Automatic verification of speed-independent circuit designs using the Circal system -- Correct compilation of specifications to deterministic asynchronous circuits -- DDD-FM9001: Derivation of a verified microprocessor -- Calculational derivation of a counter with bounded response time -- Towards a provably correct hardware implementation of occam -- Rewriting with constraints in T-ruby -- Embedding hardware verification within a commercial design framework -- An approach to formalization of data flow graphs.
520 _aThese proceedings contain the papers presented at the Advanced Research Working Conference on Correct Hardware Design Methodologies, held in Arles, France, in May 1993, and organized by the ESPRIT Working Group 6018 CHARME-2and the Universit de Provence, Marseille, in cooperation with IFIP Working Group 10.2. Formal verification is emerging as a plausible alternative to exhaustive simulation for establishing correct digital hardware designs. The validation of functional and timing behavior is a major bottleneck in current VLSI design systems, slowing the arrival of products in the marketplace with its associated increase in cost. From being a predominantly academic area of study until a few years ago, formal design and verification techniques are now beginning to migrate into industrial use. As we are now witnessing an increase in activity in this area in both academia and industry, the aim of this working conference was to bring together researchers and users from both communities.
650 0 _aComputer science.
650 0 _aMicroprogramming.
650 0 _aMemory management (Computer science).
650 0 _aData transmission systems.
650 0 _aLogic design.
650 0 _aElectronics.
650 1 4 _aComputer Science.
650 2 4 _aControl Structures and Microprogramming.
650 2 4 _aArithmetic and Logic Structures.
650 2 4 _aMemory Structures.
650 2 4 _aInput/Output and Data Communications.
650 2 4 _aLogic Design.
650 2 4 _aElectronics and Microelectronics, Instrumentation.
700 1 _aMilne, George J.
_eeditor.
700 1 _aPierre, Laurence.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783540567783
786 _dSpringer
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v683
856 4 0 _uhttp://dx.doi.org/10.1007/BFb0021709
942 _2EBK7438
_cEBK
999 _c36732
_d36732