000 05936nam a22005175i 4500
001 978-3-540-69557-8
003 DE-He213
005 20160624102058.0
007 cr nn 008mamaa
008 121227s1997 gw | s |||| 0|eng d
020 _a9783540695578
_9978-3-540-69557-8
024 7 _a10.1007/3-540-63465-7
_2doi
050 4 _aQA75.5-76.95
050 4 _aTK7885-7895
072 7 _aUK
_2bicssc
072 7 _aCOM067000
_2bisacsh
082 0 4 _a004
_223
245 1 0 _aField-Programmable Logic and Applications
_h[electronic resource] :
_b7th International Workshop, FPL '97 London, UK, September 1–3, 1997 Proceedings /
_cedited by Wayne Luk, Peter Y. K. Cheung, Manfred Glesner.
260 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1997.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1997.
300 _aXII, 512 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v1304
505 0 _aMulticontext dynamic reconfiguration and real-time probing on a novel mixed signal programmable device with on-chip microprocessor -- CAD-oriented FPGA and dedicated CAD system for telecommunications -- Rothko: A three dimensional FPGA architecture, its fabrication, and design tools -- Extending dynamic circuit switching to meet the challenges of new FPGA architectures -- Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs -- Implementation of pipelined multipliers on Xilinx FPGAs -- The XC620ODS development system -- Thermal monitoring on FPGAs using ring-oscillators -- A reconfigurable approach to low cost media processing -- Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research -- Stream synthesis for a wormhole run-time reconfigurable platform -- Pipeline morphing and virtual pipelines -- Parallel graph colouring using FPGAs -- Run-time compaction of FPGA designs -- Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement -- A case study of partially evaluated hardware circuits: Key-specific DES -- Run-time parameterised circuits for the Xilinx XC6200 -- Automatic identification of swappable logic units in XC6200 circuitry -- Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic -- Exploiting reconfigurability through domain-specific systems -- Technology mapping by binate covering -- VPR: a new packing, placement and routing tool for FPGA research -- Technology mapping of heterogeneous LUT-based FPGAs -- Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs -- Technology mapping of LUT based FPGAs for delay optimisation -- Automatic Mapping of Algorithms onto multiple FPGA-SRAM Modules -- FPLD HDL synthesis employing high-level evolutionary algorithm optimisation -- An hardware/software partitioning algorithm for custom computing machines -- The Java Environment for Reconfigurable Computing -- Data scheduling to increase performance of parallel accelerators -- An operating system for custom computing machines based on the Xputer paradigm -- Fast parallel implementation of DFT using configurable devices -- Enhancing fixed point DSP processor performance by adding CPLD's as coprocessing elements -- A case study of algorithm implementation in reconfigurable hardware and software -- A reconfigurable data-localised array for morphological algorithms -- Virtual radix array processors (V-RaAP) -- An FPGA implementation of a matched filter detector for spread spectrum communications systems -- An NTSC and PAL closed caption processor -- A 800Mpixel/sec reconfigurable image correlator on XC6216 -- A reconfigurable coprocessor for a PCI-based real time computer vision system -- Real-time stereopsis using FPGAs -- FPGAs Implementation of a digital IQ demodulator using VHDL -- Hardware compilation, configurable platforms and ASICs for self-validating sensors -- PostScript™ rendering with virtual hardware -- P4: A platform for FPGA implementation of protocol boosters -- Satisfiability on reconfigurable hardware -- Auto-configurable array for GCD computation -- Structural versus algorithmic approaches for efficient adders on xilinx 5200 FPGA -- FPGA implementation of real-time digital controllers using on-line arithmetic -- A prototyping environment for fuzzy controllers -- A reconfigurable sensor-data processing system for personal robots.
520 _aThis book constitutes the refereed proceedings of the 7th International Workshop on Field Programmable Logic and Applications, FPL '97, held in London, UK, in September 1997. The 51 revised full papers in the volume were carefully selected from a large number of high-quality papers. The book is divided into sections on devices and architectures, devices and systems, reconfiguration, design tools, custom computing and codesign, signal processing, image and video processing, sensors and graphics, color and robotics, and applications.
650 0 _aComputer science.
650 0 _aComputer hardware.
650 1 4 _aComputer Science.
650 2 4 _aComputer Hardware.
650 2 4 _aSystems and Information Theory in Engineering.
650 2 4 _aMathematical Logic and Formal Languages.
700 1 _aLuk, Wayne.
_eeditor.
700 1 _aCheung, Peter Y. K.
_eeditor.
700 1 _aGlesner, Manfred.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783540634652
786 _dSpringer
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v1304
856 4 0 _uhttp://dx.doi.org/10.1007/3-540-63465-7
942 _2EBK7257
_cEBK
999 _c36551
_d36551