000			03943nam a22005895i 4500
001			978-3-540-69338-3
003			DE-He213
005			20160624102056.0
007			cr nn 008mamaa
008			100301s2007 gw | s |||| 0|eng d
020			_a9783540693383 _9978-3-540-69338-3
024	7		_a10.1007/978-3-540-69338-3 _2doi
050		4	_aQA76.9.C62
072		7	_aUMB _2bicssc
072		7	_aUYF _2bicssc
072		7	_aCOM036000 _2bisacsh
082	0	4	_a004 _223
245	1	0	_aHigh Performance Embedded Architectures and Compilers _h[electronic resource] : _bSecond International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / _cedited by Koen Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer.
260		1	_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c2007.
264		1	_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c2007.
300			_aXI, 307 p. Also available online. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aLecture Notes in Computer Science, _x0302-9743 ; _v4367
505	0		_aInvited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints.
650		0	_aComputer science.
650		0	_aData transmission systems.
650		0	_aLogic design.
650		0	_aComputer Communication Networks.
650	1	4	_aComputer Science.
650	2	4	_aArithmetic and Logic Structures.
650	2	4	_aProcessor Architectures.
650	2	4	_aInput/Output and Data Communications.
650	2	4	_aLogic Design.
650	2	4	_aComputer Communication Networks.
650	2	4	_aProgramming Languages, Compilers, Interpreters.
700	1		_aBosschere, Koen. _eeditor.
700	1		_aKaeli, David. _eeditor.
700	1		_aStenström, Per. _eeditor.
700	1		_aWhalley, David. _eeditor.
700	1		_aUngerer, Theo. _eeditor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783540693376
786			_dSpringer
830		0	_aLecture Notes in Computer Science, _x0302-9743 ; _v4367
856	4	0	_uhttp://dx.doi.org/10.1007/978-3-540-69338-3
942			_2EBK7198 _cEBK
999			_c36492 _d36492