000 | 05742nam a22005895i 4500 | ||
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001 | 978-3-540-68599-9 | ||
003 | DE-He213 | ||
005 | 20160624102050.0 | ||
007 | cr nn 008mamaa | ||
008 | 121227s1996 gw | s |||| 0|eng d | ||
020 |
_a9783540685999 _9978-3-540-68599-9 |
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024 | 7 |
_a10.1007/3-540-61474-5 _2doi |
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050 | 4 | _aQA76.9.L63 | |
050 | 4 | _aQA76.5913 | |
050 | 4 | _aQA76.63 | |
072 | 7 |
_aUM _2bicssc |
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072 | 7 |
_aUYF _2bicssc |
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072 | 7 |
_aCOM051000 _2bisacsh |
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_aCOM036000 _2bisacsh |
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082 | 0 | 4 |
_a005.1015113 _223 |
245 | 1 | 0 |
_aComputer Aided Verification _h[electronic resource] : _b8th International Conference, CAV '96 New Brunswick, NJ, USA, July 31– August 3, 1996 Proceedings / _cedited by Rajeev Alur, Thomas A. Henzinger. |
260 | 1 |
_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c1996. |
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264 | 1 |
_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c1996. |
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300 |
_aXIII, 479 p. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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_atext file _bPDF _2rda |
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490 | 1 |
_aLecture Notes in Computer Science, _x0302-9743 ; _v1102 |
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505 | 0 | _aSymbolic verification of communication protocols with infinite state spaces using QDDs -- A conjunctively decomposed boolean representation for symbolic model checking -- Symbolic model checking using algebraic geometry -- A partition refinement algorithm for the ?-calculus -- Polynomial time algorithms for testing probabilistic bisimulation and simulation -- Pushdown processes: Games and model checking -- Module checking -- Automatic verification of parameterized synchronous systems -- HORNSAT, model checking, verification and games -- Verifying the SRT division algorithm using theorem proving techniques -- Modular verification of SRT division -- Mechanically verifying a family of multiplier circuits -- Verifying systems with replicated components in mur? -- Verification of arithmetic circuits by comparing two similar circuits -- Automated deduction and formal methods -- A platform for combining deductive with algorithmic verification -- Verifying invariants using theorem proving -- Deductive model checking -- Automated verification by induction with associative-commutative operators -- Analysis of timed systems based on time-abstracting bisimulations -- Verification of an Audio Protocol with bus collision using Uppaal -- Selective quantitative analysis and interval model checking: Verifying different facets of a system -- Verifying continuous time Markov chains -- Verifying safety properties of differential equations -- Temporal verification by diagram transformations -- Protocol verification by aggregation of distributed transactions -- Atomicity refinement and trace reduction theorems -- Powerful techniques for the automatic generation of invariants -- Saving space by fully exploiting invisible transitions -- Using on-the-fly verification techniques for the generation of test suites -- Automatic translation of natural language system specifications into temporal logic -- Verification of fair transition systems -- The state of Spin -- The Mur ? verification system -- The NCSU Concurrency Workbench -- The Concurrency Factory: A development environment for concurrent systems -- XVERSA: An integrated graphical and textual toolset for the specification and analysis of resource-bound real-time systems -- EVP: Integration of FDTs for the analysis and verification of communication protocols -- PVS: Combining specification, proof checking, and model checking -- STeP: Deductive-algorithmic verification of reactive and real-time systems -- Symbolic model checking -- COSPAN -- VIS: A system for verification and synthesis -- MDG tools for the verification of RTL designs -- CADP a protocol validation and verification toolbox -- The FC2TOOLS set -- The Real-Time Graphical Interval Logic toolset -- The METAFrame'95 environment -- Verification Support Environment -- Marrella: A tool for simulation and verification -- Verifying the safety of a practical concurrent garbage collector -- Verification by behaviour abstraction. | |
520 | _aThis book constitutes the refereed proceedings of the 8th International Conference on Computer Aided Verification, CAV '96, held in New Brunswick, NJ, USA, in July/August 1996 as part of the FLoC '96 federated conference. The volume presents 32 revised full research contributions selected from a total of 93 submissions; also included are 20 carefully selected descriptions of tools and case studies. The set of papers reports the state-of-the-art of the theory and practice of computer assisted formal analysis methods for software and hardware systems; a certain emphasis is placed on verification tools and the algorithms and techniques that are needed for their implementation. | ||
650 | 0 | _aComputer science. | |
650 | 0 | _aSoftware engineering. | |
650 | 0 | _aLogic design. | |
650 | 0 | _aArtificial intelligence. | |
650 | 1 | 4 | _aComputer Science. |
650 | 2 | 4 | _aLogics and Meanings of Programs. |
650 | 2 | 4 | _aSoftware Engineering. |
650 | 2 | 4 | _aMathematical Logic and Formal Languages. |
650 | 2 | 4 | _aSpecial Purpose and Application-Based Systems. |
650 | 2 | 4 | _aArtificial Intelligence (incl. Robotics). |
700 | 1 |
_aAlur, Rajeev. _eeditor. |
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700 | 1 |
_aHenzinger, Thomas A. _eeditor. |
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710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9783540614746 |
786 | _dSpringer | ||
830 | 0 |
_aLecture Notes in Computer Science, _x0302-9743 ; _v1102 |
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856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/3-540-61474-5 |
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_2EBK7041 _cEBK |
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_c36335 _d36335 |