000 05774nam a22005775i 4500
001 978-3-540-48683-1
003 DE-He213
005 20160624102036.0
007 cr nn 008mamaa
008 121227s1999 gw | s |||| 0|eng d
020 _a9783540486831
_9978-3-540-48683-1
024 7 _a10.1007/3-540-48683-6
_2doi
050 4 _aQA76.9.L63
050 4 _aQA76.5913
050 4 _aQA76.63
072 7 _aUM
_2bicssc
072 7 _aUYF
_2bicssc
072 7 _aCOM051000
_2bisacsh
072 7 _aCOM036000
_2bisacsh
082 0 4 _a005.1015113
_223
245 1 0 _aComputer Aided Verification
_h[electronic resource] :
_b11th International Conference, CAV’99 Trento, Italy, July 6–10, 1999 Proceedings /
_cedited by Nicolas Halbwachs, Doron Peled.
260 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1999.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1999.
300 _aXIV, 506 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v1633
505 0 _aTutorials and Invited Papers -- Alternative Approaches to Hardware Verification -- The Compositional Specification of Timed Systems — A Tutorial -- Timed Automata -- Ståalmarck’s Method with Extensions to Quantified Boolean Formulas -- Verification of Parameterized Systems by Dynamic Induction -- Formal Methods for Conformance Testing: Theory Can Be Practical -- Processor Verification -- Proof of Correctness of a Processor with Reorder Buffer Using the Completion Functions Approach -- Verifying Safety Properties of a PowerPC? Microprocessor Using Symbolic Model Checking without BDDs -- Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists -- Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study -- Protocol Verification and Testing -- Automated Verification of a Parametric Real-Time Program: The ABR Conformance Protocol -- Test Generation Derived from Model-Checking -- Latency Insensitive Protocols -- Infinite State Space -- Handling Global Conditions in Parametrized System Verification -- Verification of Infinite-State Systems by Combining Abstraction and Reachability Analysis -- Experience with Predicate Abstraction -- Theory of Verification -- Model Checking of Safety Properties -- A Complete Finite Prefix for Process Algebra -- The Mathematical Foundation of Symbolic Trajectory Evaluation -- Assume-Guarantee Refinement between Different Time Scales -- Linear Temporal Logic -- Efficient Decision Procedures for Model Checking of Linear Time Logic Properties -- Stutter-Invariant Languages, ?-Automata, and Temporal Logic -- Improved Automata Generation for Linear Temporal Logic -- Modeling of Systems -- On the Representation of Probabilities over Structured Domains -- Model Checking Partial State Spaces with 3-Valued Temporal Logics -- Elementary Microarchitecture Algebra -- Verifying Sequential Consistency on Shared-Memory Multiprocessor Systems -- Symbolic Model-Checking -- Stepwise CTL Model Checking of State/Event Systems -- Optimizing Symbolic Model Checking for Constraint-Rich Models -- Efficient Timed Reachability Analysis Using Clock Difference Diagrams -- Theorem Proving -- Mechanizing Proofs of Computation Equivalence -- Linking Theorem Proving and Model-Checking with Well-Founded Bisimulation -- Automatic Verification of Combinational and Pipelined FFT Circuits -- Automata-Theoretic Methods -- Efficient Analysis of Cyclic Definitions -- A Theory of Restrictions for Logics and Automata -- Model Checking Based on Sequential ATPG -- Automatic Verification of Abstract State Machines -- Abstraction -- Abstract and Model Check while You Prove -- Deciding Equality Formulas by Small Domains Instantiations -- Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions -- Tool Presentations -- A Toolbox for the Analysis of Discrete Event Dynamic Systems -- TIPPtool: Compositional Specification and Analysis of Markovian Performance Models -- Java Bytecode Verification by Model Checking -- NuSMV: A New Symbolic Model Verifier -- PIL/SETHEO: A Tool for the Automatic Analysis of Authentication Protocols.
520 _aThis book constitutes the refereed proceedings of the 11th International Conference on Computer Aided Verification, CAV'99, held in Trento, Italy in July 1999 as part of FLoC'99. The 34 revised full papers presented were carefully reviewed and selected from a total of 107 submissions. Also included are six invited contributions and five tool presentations. The book is organized in topical sections on processor verification, protocol verification and testing, infinite state spaces, theory of verification, linear temporal logic, modeling of systems, symbolic model checking, theorem proving, automata-theoretic methods, and abstraction.
650 0 _aComputer science.
650 0 _aLogic design.
650 0 _aSoftware engineering.
650 1 4 _aComputer Science.
650 2 4 _aLogics and Meanings of Programs.
650 2 4 _aSoftware Engineering.
650 2 4 _aMathematical Logic and Formal Languages.
650 2 4 _aLogic Design.
650 2 4 _aModels and Principles.
700 1 _aHalbwachs, Nicolas.
_eeditor.
700 1 _aPeled, Doron.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783540662020
786 _dSpringer
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v1633
856 4 0 _uhttp://dx.doi.org/10.1007/3-540-48683-6
942 _2EBK6547
_cEBK
999 _c35841
_d35841