000 04386nam a22004935i 4500
001 978-3-540-47902-4
003 DE-He213
005 20160624102027.0
007 cr nn 008mamaa
008 121227s1993 gw | s |||| 0|eng d
020 _a9783540479024
_9978-3-540-47902-4
024 7 _a10.1007/3-540-57091-8
_2doi
050 4 _aQA76.9.L63
072 7 _aUYF
_2bicssc
072 7 _aCOM036000
_2bisacsh
082 0 4 _a621.395
_223
245 1 0 _aField-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping
_h[electronic resource] :
_bSecond International Workshop on Field-Programmable Logic and Applications Vienna, Austria, August 31 – September 2, 1992 Selected Papers /
_cedited by Herbert Grünbacher, Reiner W. Hartenstein.
260 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1993.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1993.
300 _aIX, 223 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v705
505 0 _aOverview of complex array-based PLDs -- Technologies and utilization of Field Programmable Gate Arrays -- Some considerations on Field Programmable Gate Arrays and their impact on system design -- SRAM-based FPGAs ease system verification -- MONTAGE: An FPGA for synchronous and asynchronous circuits -- ORCA: A new architecture for high-performance FPGAs -- Patching method for lookup-table type FPGA's -- Automatic one-hot re-encoding for FPGAs -- Minimization of permuted Reed-Muller Trees for cellular logic programmable Gate arrays -- Self-organizing Kohonen maps for FPGA placement -- High level synthesis in an FPGA-based computer aided prototyping environment -- New application of FPGAs to programmable digital communication circuits -- FPGA based logic synthesis of squarers using VHDL -- Optimized fuzzy controller architecture for field programmable gate arrays -- A real-time kernel — Rapid prototyping with VHDL and FPGAs -- JAPROC — A 8 bit micro controller design and its test environment -- Chameleon: A workstation of a different colour -- A highly parallel FPGA-based machine and its formal verification -- FPGA based self-test with deterministic test patterns -- FPGA implementation of systolic sequence alignment -- Using FPGAs to prototype a self-timed computer -- Using FPGAs to implement a reconfigurable highly parallel computer -- Novel high performance machine paradigms and fast-turnaround ASIC design methods: A consequence of, and, a challenge to, field-programmable logic.
520 _aThis book contains papers first presented at the Second International Workshop on Field-Programmable Logic and Applications (FPL '92), held in Vienna, Austria, in August-September 1992. The growing importance of field-programmable devices, especially of field-programmable gate arrays, is demonstrated by the increased number of papers submitted in 1992. Of the 70 papers submitted, 23 were selected for this book. The first three papers were invited and discuss strategic issues and give surveys. Three papers deal with new FPGA architectures and five papers introduce methods and tools. The last twelve papers report applications focusing on rapid prototyping or new FPGA-based computer architectures. The invited papersare: "Overview of complex array-based PLDs" by G. Biehl; "Technologies and utilization of field programmable gate arrays" by J. Isoaho, A. Nummela, andH. Tenhunen; and "Some considerations on field-programmable gate arrays and their impact on system design" by A. Sangiovanni-Vincentelli.
650 0 _aComputer science.
650 0 _aLogic design.
650 0 _aElectronics.
650 1 4 _aComputer Science.
650 2 4 _aLogic Design.
650 2 4 _aElectronics and Microelectronics, Instrumentation.
700 1 _aGrünbacher, Herbert.
_eeditor.
700 1 _aHartenstein, Reiner W.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783540570912
786 _dSpringer
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v705
856 4 0 _uhttp://dx.doi.org/10.1007/3-540-57091-8
942 _2EBK6228
_cEBK
999 _c35522
_d35522