000 | 03673nam a22004695i 4500 | ||
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001 | 978-3-540-47144-8 | ||
003 | DE-He213 | ||
005 | 20160624102020.0 | ||
007 | cr nn 008mamaa | ||
008 | 121227s1987 gw | s |||| 0|eng d | ||
020 |
_a9783540471448 _9978-3-540-47144-8 |
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024 | 7 |
_a10.1007/3-540-17943-7 _2doi |
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050 | 4 | _aTK7895.M5 | |
072 | 7 |
_aUYF _2bicssc |
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072 | 7 |
_aCOM011000 _2bisacsh |
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082 | 0 | 4 |
_a004.1 _223 |
245 | 1 | 0 |
_aPARLE Parallel Architectures and Languages Europe _h[electronic resource] : _bVolume I: Parallel Architectures Eindhoven, The Netherlands, June 15–19, 1987 Proceedings / _cedited by J. W. Bakker, A. J. Nijman, P. C. Treleaven. |
260 | 1 |
_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c1987. |
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264 | 1 |
_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c1987. |
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300 |
_aXIV, 490 p. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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_aonline resource _bcr _2rdacarrier |
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_atext file _bPDF _2rda |
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490 | 1 |
_aLecture Notes in Computer Science, _x0302-9743 ; _v258 |
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505 | 0 | _aLearning translation invariant recognition in a massively parallel networks -- Trace theory and systolic computations -- Boltzmann machines and their applications -- Cobweb-2: Structured specification of a wafer-scale supercomputer -- A novel deadlock free and starvation free packet switching communication processor -- A parallel architecture for signal understanding through inference on uncertain data -- An axiomatic approach to the specification of distributed computer architectures -- Computing on a systolic screen: Hulls, contours and applications -- Multiprocessor systems programming in a high-level data-flow language -- The twisted cube -- An implemented method for incremental systolic design -- The use of parallel functions in system design -- The translation of processes into circuits -- Mapping strategies in message based multiprocessor systems -- Hardware memory management for large knowledge bases -- Transputer-based experiments with the ZAPP architecture -- Synthesis of systolic arrays for inductive problems -- Practical parallelism using transputer arrays -- Systolic array synthesis by static analysis of program dependencies -- Specification of a pipelined event driven simulator using FP2 -- A layered emulator for design evaluation of MIMD multiprocessors with shared memory -- The Alliant FX/Series: A language driven architecture for parallel processing of dusty deck fortran -- Emulating digital logic using transputer networks (very high parallelism = simplicity = performance) -- A two-level approach to logic plus functional programming integration -- Overview of a parallel reduction machine project -- An overview of DDC: Delta driven computer -- Design and implementation of a parallel inference machine for first order logic: an overview -- Multi-level simulator for VLSI -- The DOOM system and its applications: A survey of esprit 415 subproject A, philips research laboratories. | |
650 | 0 | _aComputer science. | |
650 | 1 | 4 | _aComputer Science. |
650 | 2 | 4 | _aProcessor Architectures. |
650 | 2 | 4 | _aProgramming Languages, Compilers, Interpreters. |
700 | 1 |
_aBakker, J. W. _eeditor. |
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700 | 1 |
_aNijman, A. J. _eeditor. |
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700 | 1 |
_aTreleaven, P. C. _eeditor. |
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710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9783540179436 |
786 | _dSpringer | ||
830 | 0 |
_aLecture Notes in Computer Science, _x0302-9743 ; _v258 |
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856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/3-540-17943-7 |
942 |
_2EBK5989 _cEBK |
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_c35283 _d35283 |