000 06038nam a22006015i 4500
001 978-3-540-46763-2
003 DE-He213
005 20160624102018.0
007 cr nn 008mamaa
008 121227s1992 gw | s |||| 0|eng d
020 _a9783540467632
_9978-3-540-46763-2
024 7 _a10.1007/3-540-55179-4
_2doi
050 4 _aQA76.9.L63
050 4 _aQA76.5913
050 4 _aQA76.63
072 7 _aUM
_2bicssc
072 7 _aUYF
_2bicssc
072 7 _aCOM051000
_2bisacsh
072 7 _aCOM036000
_2bisacsh
082 0 4 _a005.1015113
_223
245 1 0 _aComputer Aided Verification
_h[electronic resource] :
_b3rd International Workshop, CAV '91 Aalborg, Denmark, July 1–4, 1991 Proceedings /
_cedited by Kim G. Larsen, Arne Skou.
260 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1992.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1992.
300 _aXI, 493 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v575
505 0 _aTaming infinite state spaces -- Silence is golden: Branching bisimilarity is decidable for context-free processes -- Computing distinguishing formulas for branching bisimulation -- Compositional checking of satisfaction -- An action based framework for verifying logical and behavioural properties of concurrent systems -- A linear-time model-checking algorithm for the alternation-free modal mu-calculus -- Automatic temporal verification of buffer systems -- Mechanically checked proofs of kernel specifications -- A top down approach to the formal specification of SCI cache coherence -- Integer programming in the analysis of concurrent systems -- The lotos model of a fault protected system and its verification using a petri net based approach -- Error diagnosis in finite communicating systems -- Temporal precondition verification of design transformations -- PAM: A process algebra manipulator -- The Concurrency Workbench with priorities -- A proof assistant for PSF -- Avoiding state explosion by composition of minimal covering graphs -- “On the fly” verification of behavioural equivalences and preorders -- Bounded-memory algorithms for verification on-the-fly -- Generating BDDs for symbolic model checking in CCS -- Vectorized symbolic model checking of computation tree logic for sequential machine verification -- Functional extension of symbolic model checking -- An automated proof technique for finite-state machine equivalence -- From data structure to process structure -- Checking for language inclusion using simulation preorders -- A semantic driven method to check the fineteness of CCS processes -- Using the HOL prove assistant for proving the correctness of term rewriting rules reducing terms of sequential behavior -- Mechanizing a proof by induction of process algebra specifications in higher order logic -- A two-level formal verification methodology using HOL and COSMOS -- Efficient algorithms for verification of equivalences for probabilistic processes -- Partial-order model checking: A guide for the perplexed -- Using partial orders for the efficient verification of deadlock freedom and safety properties -- Complexity results for POMSET languages -- Mechanically verifying safety and liveness properties of delay insensitive circuits -- Automating most parts of hardware proofs in HOL -- An overview and synthesis on timed process algebras -- Minimum and maximum delay problems in realtime systems -- Formal verification of speed-dependent asynchronous circuits using symbolic model checking of Branching Time Regular Temporal Logic -- Verifying properties of HMS machine specifications of real-time systems -- A linear time process algebra -- Deciding properties of regular real timed processes -- An algebra of Boolean processes -- Comparing generic state machines -- An automata theoretic approach to Temporal Logic.
520 _aThis volume contains the proceedings of the third International Workshop on Computer Aided Verification, CAV '91, held in Aalborg, Denmark, July 1-4, 1991. The objective of this series of workshops is to bring together researchers and practitioners interested in the development and use of methods, tools and theories for automatic verification of (finite) state systems. The workshop provides a unique opportunity for comparing the numerous verification methods and associated verification tools, and the extent to which they may be utilized in application design. The emphasis is not only on new research results but also on the application of existing results to real verification problems. The papers in the volume areorganized into sections on equivalence checking, model checking, applications, tools for process algebras, the state explosion problem, symbolic model checking, verification and transformation techniques, higher order logic, partial order approaches, hardware verification, timed specification and verification, and automata.
650 0 _aComputer science.
650 0 _aComputer Communication Networks.
650 0 _aSoftware engineering.
650 0 _aLogic design.
650 0 _aLogic, Symbolic and mathematical.
650 1 4 _aComputer Science.
650 2 4 _aLogics and Meanings of Programs.
650 2 4 _aMathematical Logic and Formal Languages.
650 2 4 _aSpecial Purpose and Application-Based Systems.
650 2 4 _aComputer Communication Networks.
650 2 4 _aMathematical Logic and Foundations.
700 1 _aLarsen, Kim G.
_eeditor.
700 1 _aSkou, Arne.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783540551799
786 _dSpringer
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v575
856 4 0 _uhttp://dx.doi.org/10.1007/3-540-55179-4
942 _2EBK5890
_cEBK
999 _c35184
_d35184