000 05430nam a22005535i 4500
001 978-3-540-40922-9
003 DE-He213
005 20160624101948.0
007 cr nn 008mamaa
008 121227s2000 gw | s |||| 0|eng d
020 _a9783540409229
_9978-3-540-40922-9
024 7 _a10.1007/3-540-40922-X
_2doi
050 4 _aQA75.5-76.95
050 4 _aTK7885-7895
072 7 _aUK
_2bicssc
072 7 _aCOM067000
_2bisacsh
082 0 4 _a004
_223
245 1 0 _aFormal Methods in Computer-Aided Design
_h[electronic resource] :
_bThird International Conference, FMCAD 2000 Austin, TX, USA, November 1–3, 2000 Proceedings /
_cedited by Warren A. Hunt, Steven D. Johnson.
260 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c2000.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c2000.
300 _aXII, 552 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v1954
505 0 _aApplications of Hierarchical Verification in Model Checking -- Applications of Hierarchical Verification in Model Checking -- Invited Talk -- Trends in Computing -- Invited Paper -- A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon TM Processor -- Contributed Papers -- An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps -- Automated Refinement Checking for Asynchronous Processes -- Border-Block Triangular Form and Conjunction Schedule in Image Computation -- B2M: A Semantic Based Tool for BLIF Hardware Descriptions -- Checking Safety Properties Using Induction and a SAT-Solver -- Combining Stream-Based and State-Based Verification Techniques -- A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles -- Correctness of Pipelined Machines -- Do You Trust Your Model Checker? -- Executable Protocol Specification in ESL -- Formal Verification of Floating Point Trigonometric Functions -- Hardware Modeling Using Function Encapsulation -- A Methodology for the Formal Analysis of Asynchronous Micropipelines -- A Methodology for Large-Scale Hardware Verification -- Model Checking Synchronous Timing Diagrams -- Model Reductions and a Case Study -- Modeling and Parameters Synthesis for an Air TrafficManagement System -- Monitor-Based Formal Specification of PCI -- SAT-Based Image Computation with Application in Reachability Analysis -- SAT-Based Verification without State Space Traversal -- Scalable Distributed On-the-Fly Symbolic Model Checking -- The Semantics of Verilog Using Transition System Combinators -- Sequential Equivalence Checking by Symbolic Simulation -- Speeding Up Image Computation by Using RTL Information -- Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs -- Symbolic Simulation with Approximate Values -- A Theory of Consistency for Modular Synchronous Systems -- Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods -- Visualizing System Factorizations with Behavior Tables.
520 _aThe biannual Formal Methods in Computer Aided Design conference (FMCAD 2000)is the third in a series of conferences under that title devoted to the use of discrete mathematical methods for the analysis of computer hardware and so- ware. The work reported in this book describes the use of modeling languages and their associated automated analysis tools to specify and verify computing systems. Functional veric ation has become one of the principal costs in a modern computer design e ort. In addition,verica tion of circuit models, timing,power, etc., requires even more eo rt. FMCAD provides a venue for academic and - dustrial researchers and practitioners to share their ideas and experiences of using discrete mathematical modeling and veric ation. It is noted with interest by the conference chairmen how this area has grown from just a few people 15 years ago to a vibrant area of research, development, and deployment. It is clear that these methods are helping reduce the cost of designing computing systems. As an example of this potential cost reduction, we have invited David Russino of Advanced Micro Devices, Inc. to describe his veric ation of ?oating-point - gorithms being used in AMD microprocessors. The program includes 30 regular presentations selected from 63 submitted papers.
650 0 _aComputer science.
650 0 _aComputer hardware.
650 0 _aLogic design.
650 0 _aArtificial intelligence.
650 1 4 _aComputer Science.
650 2 4 _aComputer Hardware.
650 2 4 _aLogics and Meanings of Programs.
650 2 4 _aMathematical Logic and Formal Languages.
650 2 4 _aArtificial Intelligence (incl. Robotics).
650 2 4 _aSystems and Information Theory in Engineering.
700 1 _aHunt, Warren A.
_eeditor.
700 1 _aJohnson, Steven D.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783540412199
786 _dSpringer
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v1954
856 4 0 _uhttp://dx.doi.org/10.1007/3-540-40922-X
942 _2EBK4828
_cEBK
999 _c34122
_d34122