000 05917nam a22006135i 4500
001 978-3-540-38394-9
003 DE-He213
005 20160624101939.0
007 cr nn 008mamaa
008 121227s1991 gw | s |||| 0|eng d
020 _a9783540383949
_9978-3-540-38394-9
024 7 _a10.1007/BFb0023712
_2doi
050 4 _aQA76.9.L63
050 4 _aQA76.5913
050 4 _aQA76.63
072 7 _aUM
_2bicssc
072 7 _aUYF
_2bicssc
072 7 _aCOM051000
_2bisacsh
072 7 _aCOM036000
_2bisacsh
082 0 4 _a005.1015113
_223
245 1 0 _aComputer-Aided Verification
_h[electronic resource] :
_b2nd International Conference, CAV '90 New Brunswick, NJ, USA, June 18–21, 1990 Proceedings /
_cedited by Edmund M. Clarke, Robert P. Kurshan.
260 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1991.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1991.
300 _aXIV, 378 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v531
505 0 _aTemporal logic model checking: Two techniques for avoiding the state explosion problem -- Automatic verification of extensions of hardware descriptions -- Papetri : Environment for the analysis of PETRI nets -- Verifying temporal properties of sequential machines without building their state diagrams -- Formal verification of digital circuits using symbolic ternary system models -- Vectorized model checking for computation tree logic -- to a computational theory and implementation of sequential hardware equivalence -- Auto/autograph -- A data path verifier for register transfer level using temporal logic language Tokio -- The use of model checking in ATPG for sequential circuits -- Compositional design and verification of communication protocols, using labelled petri nets -- Issues arising in the analysis of L.0 -- Automated RTL verification based on predicate calculus -- On using protean to verify ISO FTAM protocol -- Quantitative temporal reasoning -- Using partial-order semantics to avoid the state explosion problem in asynchronous systems -- A stubborn attack on state explosion -- Using optimal simulations to reduce reachability graphs -- Using partial orders to improve automatic verification methods -- Compositional minimization of finite state systems -- Minimal model generation -- A context dependent equivalence relation between kripke structures -- The modular framework of computer-aided verification -- Verifying liveness properties by verifying safety properties -- Memory efficient algorithms for the verification of temporal properties -- A unified approach to the deadlock detection problem in networks of communicating finite state machines -- Branching time regular temporal logic for model checking with linear time complexity -- The algebraic feedback product of automata -- Synthesizing processes and schedulers from temporal specifications -- Task-driven supervisory control of discrete event systems -- A proof lattice-based technique for analyzing liveness of resource controllers -- Verification of a multiprocessor cache protocol using simulation relations and higher-order logic (summary) -- Computer assistance for program refinement -- Program verification by symbolic execution of hyperfinite ideal machines -- Extension of the Karp and miller procedure to lotos specifications -- An algebra for delay-insensitive circuits -- Finiteness conditions and structural construction of automata for all process algebras -- On automatically explaining bisimulation inequivalence.
520 _aThis volume contains the proceedings of the second workshop on Computer Aided Verification, held at DIMACS, Rutgers University, June 18-21, 1990. Itfeatures theoretical results that lead to new or more powerful verification methods. Among these are advances in the use of binary decision diagrams, dense time, reductions based upon partial order representations and proof-checking in controller verification. The motivation for holding a workshop on computer aided verification was to bring together work on effective algorithms or methodologies for formal verification - as distinguished, say,from attributes of logics or formal languages. The considerable interest generated by the first workshop, held in Grenoble, June 1989 (see LNCS 407), prompted this second meeting. The general focus of this volume is on the problem of making formal verification feasible for various models of computation. Specific emphasis is on models associated with distributed programs, protocols, and digital circuits. The general test of algorithm feasibility is to embed it into a verification tool, and exercise that tool on realistic examples: the workshop included sessionsfor the demonstration of new verification tools.
650 0 _aComputer science.
650 0 _aComputer Communication Networks.
650 0 _aSoftware engineering.
650 0 _aLogic design.
650 0 _aLogic, Symbolic and mathematical.
650 1 4 _aComputer Science.
650 2 4 _aLogics and Meanings of Programs.
650 2 4 _aMathematical Logic and Formal Languages.
650 2 4 _aSoftware Engineering.
650 2 4 _aSpecial Purpose and Application-Based Systems.
650 2 4 _aComputer Communication Networks.
650 2 4 _aMathematical Logic and Foundations.
700 1 _aClarke, Edmund M.
_eeditor.
700 1 _aKurshan, Robert P.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783540544777
786 _dSpringer
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v531
856 4 0 _uhttp://dx.doi.org/10.1007/BFb0023712
942 _2EBK4478
_cEBK
999 _c33772
_d33772