000 05507nam a22006015i 4500
001 978-3-540-32272-6
003 DE-He213
005 20160624101925.0
007 cr nn 008mamaa
008 101222s2005 gw | s |||| 0|eng d
020 _a9783540322726
_9978-3-540-32272-6
024 7 _a10.1007/11587514
_2doi
050 4 _aQA76.9.C62
072 7 _aUMB
_2bicssc
072 7 _aUYF
_2bicssc
072 7 _aCOM036000
_2bisacsh
082 0 4 _a004
_223
245 1 0 _aHigh Performance Embedded Architectures and Compilers
_h[electronic resource] :
_bFirst International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005. Proceedings /
_cedited by Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer.
260 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c2005.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c2005.
300 _aXIV, 318 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v3793
505 0 _aInvited Program -- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications -- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges -- Software Defined Radio – A High Performance Embedded Challenge -- I Analysis and Evaluation Techniques -- A Practical Method for Quickly Evaluating Program Optimizations -- Efficient Sampling Startup for Sampled Processor Simulation -- Enhancing Network Processor Simulation Speed with Statistical Input Sampling -- II Novel Memory and Interconnect Architectures -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation -- Streaming Sparse Matrix Compression/Decompression -- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs -- III Security Architecture -- Memory-Centric Security Architecture -- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management -- Arc3D: A 3D Obfuscation Architecture -- IV Novel Compiler and Runtime Techniques -- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations -- Induction Variable Analysis with Delayed Abstractions -- Garbage Collection Hints -- V DomainSpecificArchitectures -- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors -- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture -- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems -- A Low-Power DSP-Enhanced 32-Bit EISC Processor.
520 _aAs Chairmen of HiPEAC 2005, we have the pleasure of welcoming you to the proceedings of the ?rst international conference promoted by the HiPEAC N- work of Excellence. During the last year, HiPEAC has been building its clusters of researchers in computer architecture and advanced compiler techniques for embedded and high-performance computers. Recently, the Summer School has been the seed for a fruitful collaboration of renowned international faculty and young researchers from 23 countries with fresh new ideas. Now, the conference promises to be among the premier forums for discussion and debate on these research topics. Theprestigeofasymposiumismainlydeterminedbythequalityofitstech- cal program. This ?rst programlived up to our high expectations, thanks to the largenumber of strong submissions. The ProgramCommittee received a total of 84 submissions; only 17 were selected for presentation as full-length papers and another one as an invited paper. Each paper was rigorously reviewed by three ProgramCommittee members and at least one external referee. Many reviewers spent a great amount of e?ort to provide detailed feedback. In many cases, such feedback along with constructive shepherding resulted in dramatic improvement in the quality of accepted papers. The names of the Program Committee m- bers and the referees are listed in the proceedings. The net result of this team e?ort is that the symposium proceedings include outstanding contributions by authors from nine countries in three continents. In addition to paper presentations, this ?rst HiPEAC conference featured two keynotes delivered by prominent researchers from industry and academia.
650 0 _aComputer science.
650 0 _aData transmission systems.
650 0 _aLogic design.
650 0 _aComputer Communication Networks.
650 1 4 _aComputer Science.
650 2 4 _aArithmetic and Logic Structures.
650 2 4 _aInput/Output and Data Communications.
650 2 4 _aLogic Design.
650 2 4 _aProcessor Architectures.
650 2 4 _aComputer Communication Networks.
650 2 4 _aProgramming Languages, Compilers, Interpreters.
700 1 _aConte, Tom.
_eeditor.
700 1 _aNavarro, Nacho.
_eeditor.
700 1 _aHwu, Wen-mei W.
_eeditor.
700 1 _aValero, Mateo.
_eeditor.
700 1 _aUngerer, Theo.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783540303176
786 _dSpringer
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v3793
856 4 0 _uhttp://dx.doi.org/10.1007/11587514
942 _2EBK3938
_cEBK
999 _c33232
_d33232