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001 978-0-387-34801-8
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007 cr nn 008mamaa
008 121227s1990 xxu| s |||| 0|eng d
020 _a9780387348018
_9978-0-387-34801-8
024 7 _a10.1007/0-387-97226-9
_2doi
050 4 _aQA76.635
072 7 _aUMB
_2bicssc
072 7 _aCOM067000
_2bisacsh
072 7 _aCOM041000
_2bisacsh
082 0 4 _a005.18
_223
245 1 0 _aHardware Specification, Verification and Synthesis: Mathematical Aspects
_h[electronic resource] :
_bMathematical Sciences Institute Workshop Cornell University, Ithaca, New York, USA July 5–7, 1989 Proceedings /
_cedited by Miriam Leeser, Geoffrey Brown.
260 1 _aNew York, NY :
_bSpringer New York,
_c1990.
264 1 _aNew York, NY :
_bSpringer New York,
_c1990.
300 _aVIII, 404 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v408
505 0 _aDesign for verifiability -- Verification of synchronous circuits by symbolic logic simulation -- Constraints, abstraction, and verification -- Formalising the design of an SECD chip -- Reasoning about state machines in higher-order logic -- A mechanically derived systolic implementation of pyramid initialization -- Behavior-preserving transformations for high-level synthesis -- From programs to transistors: Verifying hardware synthesis tools -- Combining engineering vigor with mathematical rigor -- Totally verified systems: Linking verified software to verified hardware -- What's in a timing discipline? Considerations in the specification and synthesis of systems with interacting asynchronous and synchronous components -- Complete trace structures -- The design of a delay-insensitive microprocessor: An example of circuit synthesis by program transformation -- Manipulating logical organization with system factorizations -- The verification of a bit-slice ALU -- Verification of a pipelined microprocessor using clio -- Verification of combinational logic in Nuprl -- Veritas+: A specification language based on type theory -- Categories for the working hardware designer.
520 _aCurrent research into formal methods for hardware design is presented in the papers in this volume. Because of the complexity of VLSI circuits, assuring design validity before circuits are manufactured is imperative. The goal of research in this area is to develop methods of improving the design process and the quality of the resulting designs. The major trend apparent at the workshop is that researchers are rapidly moving away from post hoc proof techniques with their great expense. A number of papers were presented that dealt with problems of synthesizing correct circuits and of designing with the goal of verification. Researchers are also beginning to deal with the theoretical issues of reasoning about concurrent systems and asynchronous systems, and to introduce new logical tools such as constructive type theory and category theory. Most of the research reported was performed in the United States.
650 0 _aComputer science.
650 0 _aMicroprogramming.
650 0 _aLogic design.
650 0 _aAlgebra.
650 0 _aElectronics.
650 1 4 _aComputer Science.
650 2 4 _aControl Structures and Microprogramming.
650 2 4 _aArithmetic and Logic Structures.
650 2 4 _aLogic Design.
650 2 4 _aElectronics and Microelectronics, Instrumentation.
650 2 4 _aComputation by Abstract Devices.
650 2 4 _aAlgebra.
700 1 _aLeeser, Miriam.
_eeditor.
700 1 _aBrown, Geoffrey.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9780387972268
786 _dSpringer
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v408
856 4 0 _uhttp://dx.doi.org/10.1007/0-387-97226-9
942 _2EBK2979
_cEBK
999 _c32273
_d32273