TY  - BOOK
AU  - Leeser,Miriam
AU  - Brown,Geoffrey
ED  - SpringerLink (Online service)
TI  - Hardware Specification, Verification and Synthesis: Mathematical Aspects: Mathematical Sciences Institute Workshop Cornell University, Ithaca, New York, USA July 5–7, 1989 Proceedings 
T2  - Lecture Notes in Computer Science,
SN  - 9780387348018
AV  - QA76.635 
U1  - 005.18 23
PY  - 1990///
CY  - New York, NY
PB  - Springer New York
KW  - Computer science
KW  - Microprogramming
KW  - Logic design
KW  - Algebra
KW  - Electronics
KW  - Computer Science
KW  - Control Structures and Microprogramming
KW  - Arithmetic and Logic Structures
KW  - Logic Design
KW  - Electronics and Microelectronics, Instrumentation
KW  - Computation by Abstract Devices
N1  - Design for verifiability -- Verification of synchronous circuits by symbolic logic simulation -- Constraints, abstraction, and verification -- Formalising the design of an SECD chip -- Reasoning about state machines in higher-order logic -- A mechanically derived systolic implementation of pyramid initialization -- Behavior-preserving transformations for high-level synthesis -- From programs to transistors: Verifying hardware synthesis tools -- Combining engineering vigor with mathematical rigor -- Totally verified systems: Linking verified software to verified hardware -- What's in a timing discipline? Considerations in the specification and synthesis of systems with interacting asynchronous and synchronous components -- Complete trace structures -- The design of a delay-insensitive microprocessor: An example of circuit synthesis by program transformation -- Manipulating logical organization with system factorizations -- The verification of a bit-slice ALU -- Verification of a pipelined microprocessor using clio -- Verification of combinational logic in Nuprl -- Veritas+: A specification language based on type theory -- Categories for the working hardware designer
N2  - Current research into formal methods for hardware design is presented in the papers in this volume. Because of the complexity of VLSI circuits, assuring design validity before circuits are manufactured is imperative. The goal of research in this area is to develop methods of improving the design process and the quality of the resulting designs. The major trend apparent at the workshop is that researchers are rapidly moving away from post hoc proof techniques with their great expense. A number of papers were presented that dealt with problems of synthesizing correct circuits and of designing with the goal of verification. Researchers are also beginning to deal with the theoretical issues of reasoning about concurrent systems and asynchronous systems, and to introduce new logical tools such as constructive type theory and category theory. Most of the research reported was performed in the United States
UR  - http://dx.doi.org/10.1007/0-387-97226-9
ER  -